1. Field of the Invention
The present invention relates to a method for forming a bit line, more particularly, it relates to a method for controlling the depth of the bit line and the bit line contact.
2. Description of the Related Art
FIGS. 1a to 1f are AA line cross-sections of FIG. 3 of a conventional method for forming a bit line.
In FIG. 1a, a semiconductor substrate 101 is provided. A gate oxide layer 103, a poly silicon layer 104, a nitride layer 105, and a patterned photoresist layer 106 for forming a gate are sequentially formed on the semiconductor substrate 101.
In FIG. 1b, the nitride layer 105, the poly silicon layer 104, and the gate oxide layer 103 are sequentially anisotropically etched using the photoresist layer 106 as a mask to form a nitride layer 105a, a poly silicon layer 104a, and a gate oxide layer 103a respectively. The patterned photoresist layer 106 is removed. A gate is formed by the poly silicon layer 104a and the nitride layer 105a. 
In FIG. 1c, a nitride layer is conformally formed on the surface of the semiconductor substrate 101 and the elements thereon. The nitride layer is anisotropically etched to form a spacer 107 on a sidewall of the gate.
In FIG. 1d, an oxide layer 108 and a patterned photoresist layer 109 with an opening 110 are sequentially formed on the semiconductor substrate 101. A portion of the oxide layer 108 is exposed by the opening 110.
In FIG. 1e, the oxide layer 108 is anisotropically etched using the patterned photoresist layer 109 as an etching mask to form an opening as a bit line contact. The patterned photoresist layer 109 is removed.
In FIG. 1f, a poly silicon layer 111 is formed on the oxide layer 108, and the opening is filled with the poly silicon layer 111. The poly silicon layer 111 is planarized until the surface of the oxide layer 108 is exposed. The poly silicon layer 111a in the opening is at a predetermined distance of about 300 to 3000 Å form the top of the opening. An opening 111b is formed in layer 111a. 
FIGS. 1g to 1j are BB line cross-sections of FIG. 3 of a conventional method for forming a bit line.
In FIG. 1g, a patterned photoresist layer 112 with an opening 113 is formed on the surface of the oxide layer 108, corresponding to the peripheral circuit layer 102.
In FIG. 1h, the oxide layer 108 is anisotropically etched to form an opening 114 using the patterned photoresist layer 112 as a mask. The patterned photoresist layer is removed.
In FIG. 1i, a patterned photoresist layer 115 with openings 116a and 116b is formed on the oxide layer 108.
The oxide layer 108 is anisotropically etched to form an opening with a predetermined depth using the patterned photoresist layer 115 as a mask, and then an ultra thin barrier layer 117 is formed on the surface of the openings 111b, 116, and 114. A tungsten metal layer is formed on the surface of the oxide layer 108, and the openings 111b, 116, and 114 are filled with the tungsten metal layer. The tungsten metal layer is etched back to expose the surface of the oxide layer 108, such that a tungsten metal layer 118a, 118b, and 118c are formed in the opening 111b, 116, and 114 respectively. The tungsten metal layer 118a and 118b are bit lines, and the tungsten metal layer 118c is a contact of the peripheral circuit wire.
The transmission rate is high due to tungsten's low resistance. When tungsten layers 118a, 118b, and 118c are doped with WF6 gas, gaps are created in the poly silicon layer by F ions in the WF6 gas entering thereinto.